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发帖数: 68 | 1 帮朋友转到版上,感兴趣的请直接和他联系。
Email: s*******[email protected]
Position Title: Junior Circuit Design Engineer (0-4 years’ experience)
Description/
Qualifications: RESPONSIBILITIES:
- High performance, low power custom circuit design in Digital-IP.
- Design, optimization, simulation and characterization of custom digital
circuits.
- Logic equivalence checking and transistor level function verification.
- 6T/8T/10T sram design.
- Library cells and datapath cells design.
- Knowledge of multi-port RF, ROM, CAM, TLB, L1/L2 cache design.
- Understanding device physics and parasitics.
- Layout floor planning and supervision.
MINIMUM REQUIREMENTS:
- BSEE minimum, MSEE preferred.
- Strong background in deep submicron CMOS process and device. 45nm and
beyond is preferred
- Good knowledge in high speed and low power circuit design techniques
- Familiar with Hspice, hsim, XA, Nanosim and other simulation tools
- Perl, C/C++ programming skills
- Experience in circuit simulation, schematic capture and layout
verification CAD tools.
- Must be a team player with effective written and verbal communication
skills.
- Must be able to learn quickly and work independently
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Position Title: Junior Mask Design Engineer (0-4 years’ experience)
Description/
Qualifications: JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and
custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- Knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
- Perl or unit shell programming a plus.
- Be a good team player with effective written and verbal communication
skills.
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